IPR-NIOS Altera, IPR-NIOS Datasheet - Page 83

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Programming Model
Exception Processing
December 2010 Altera Corporation
Requested Register Set
If shadow register sets are implemented on the Nios II core, the EIC specifies a
register set when it asserts an interrupt request. When it takes the interrupt, the
Nios II processor switches to the requested register set. When an interrupt has a
dedicated register set, the interrupt handler avoids the overhead of saving registers.
The method of assigning register sets to interrupts depends on the specific EIC
implementation. Register set assignments can be software-configurable.
Multiple interrupts can be configured to share a register set. In this case, the interrupt
handlers must be written so as to avoid register corruption. For example, one of the
following conditions must be true:
■
■
Typically, the Nios II processor is configured so that when it takes an interrupt, other
interrupts in the same register set are disabled. If interrupt preemption within a
register set is desired, the interrupt handler can re-enable interrupts in its register set.
By default, the Nios II processor disables maskable interrupts when it takes an
interrupt request. To enable nested interrupts, system software or the ISR itself must
re-enable interrupts after the interrupt is taken.
Alternatively, to take full advantage of nested interrupts with shadow register sets,
system software can set the config.ANI flag. When config.ANI = 1, the Nios II
processor leaves maskable interrupts enabled after it takes an interrupt.
Requested NMI Mode
Any interrupt can be nonmaskable, depending on the configuration of the EIC. An
NMI typically signals a critical system event requiring immediate handling, to ensure
either system stability or real-time performance.
status.IL and RIL are ignored for nonmaskable interrupts.
Shadow Register Sets
Although shadow register sets can be implemented independently of the EIC
interface, typically the two features are used together. Combining shadow register
sets with an appropriate EIC, you can minimize or eliminate the context switch
overhead for critical interrupts.
For the best interrupt performance, assign a dedicated register set to each of the most
time-critical interrupts. Less-critical interrupts can share register sets, provided the
ISRs are protected from register corruption as noted in
The method for mapping interrupts to register sets is specific to the particular EIC
implementation.
The interrupts cannot pre-empt one another. For example, all interrupts are at the
same level.
Registers are saved in software. For example, each interrupt handler saves its own
registers on entry, and restores them on exit.
“Requested Register
Nios II Processor Reference Handbook
Set”.
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