IPR-NIOS Altera, IPR-NIOS Datasheet - Page 191

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Assembler Macros
Assembler Macros
Table 8–4. Assembler Macros
Instruction Set Reference
December 2010 Altera Corporation
%lo(immed32)
%hi(immed32)
%hiadj(immed32)
%gprel(immed32)
Note to
(1) Refer to the
Table
Macro
8–4:
Application Binary Interface
The Nios II assembler provides macros to extract halfwords from labels and from
32-bit immediate values.
16-bit signed values or 16-bit unsigned values depending on where they are used.
When used with an instruction that requires a 16-bit signed immediate value, these
macros return a value ranging from –32768 to 32767. When used with an instruction
that requires a 16-bit unsigned immediate value, these macros return a value ranging
from 0 to 65535.
The following pages list all Nios II instruction mnemonics in alphabetical order.
Table 8–5
Table 8–5. Notation Conventions (Part 1 of 2)
X ← Y
PC ← X
PC
rA, rB, rC
prs.rA
IMMn
IMMED
X
X
0xNNMM
X : Y
σ (X)
X >> n
X << n
X & Y
n
n ..m
Extract bits [15..0] of immed32
Extract bits [31..16] of immed32
Extract bits [31..16] and adds bit 15 of immed32
Replace the immed32 address with an offset from
the global pointer
Notation
shows the notation conventions used to describe instruction operation.
chapter of the Nios II Processor Reference Handbook for more information about global pointers.
(1)
X is written with Y
The program counter (PC) is written with address X; the instruction at X is
the next instruction to execute
The address of the assembly instruction in question
One of the 32-bit general-purpose registers
General-purpose register rA in the previous register set
An n-bit immediate value, embedded in the instruction word
An immediate value
The n
Consecutive bits n through m of X
Hexadecimal notation
Bitwise concatenation
For example, (0x12 : 0x34) = 0x1234
The value of X after being sign-extended to a full register-sized signed integer
The value X after being right-shifted n bit positions
The value X after being left-shifted n bit positions
Bitwise logical AND
Description
th
Table 8–4
bit of X, where n = 0 is the LSB
lists the available macros. These macros return
Meaning
immed32 & 0xFFFF
(immed32 >> 16) & 0xFFFF
((immed32 >> 16) & 0xFFFF) +
((immed32 >> 15) & 0x1)
immed32 –_gp
Nios II Processor Reference Handbook
Operation
8–5