IPR-NIOS Altera, IPR-NIOS Datasheet - Page 147

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Nios II Core Implementation Details
Nios II/s Core
December 2010 Altera Corporation
Overview
Arithmetic Logic Unit
The resulting core is optimal for cost-sensitive, medium-performance applications.
This includes applications with large amounts of code and/or data, such as systems
running an operating system in which performance is not the highest priority.
The Nios II/s core:
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The following sections discuss the noteworthy details of the Nios II/s core
implementation. This document does not discuss low-level design issues or
implementation details that do not affect Nios II hardware or software designers.
The Nios II/s core provides several ALU options to improve the performance of
multiply, divide, and shift operations.
Multiply and Divide Performance
The Nios II/s core provides the following hardware multiplier options:
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The Nios II/s core also provides a hardware divide option that includes LE-based
divide circuitry in the ALU.
Including an ALU option improves the performance of one or more arithmetic
instructions.
Has an instruction cache, but no data cache
Can access up to 2 GB of external address space
Supports optional tightly-coupled memory for instructions
Employs a 5-stage pipeline
Performs static branch prediction
Provides hardware multiply, divide, and shift options to improve arithmetic
performance
Supports the addition of custom instructions
Supports the JTAG debug module
Supports optional JTAG debug module enhancements, including hardware
breakpoints and real-time trace
DSP Block—Includes DSP block multipliers available on the target device. This
option is available only on Altera FPGAs that have DSP Blocks.
Embedded Multipliers—Includes dedicated embedded multipliers available on
the target device. This option is available only on Altera FPGAs that have
embedded multipliers.
Logic Elements—Includes hardware multipliers built from logic element (LE)
resources.
None—Does not include multiply hardware. In this case, multiply operations are
emulated in software.
Nios II Processor Reference Handbook
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