IPR-NIOS Altera, IPR-NIOS Datasheet - Page 161

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IPR-NIOS

Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet

Specifications of IPR-NIOS

License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
Chapter 6: Nios II Processor Revision History
Core Revisions
Table 6–3. Nios II/f Core Revisions (Part 3 of 3)
Table 6–4. Nios II/s Core Revisions (Part 1 of 2)
December 2010 Altera Corporation
1.01
1.0
10.1
10.0
9.1
9.0
8.1
8.0
7.2
7.1
7.0
6.1
6.0
5.1
5.0
Version
Version
Nios II/s Core
December 2010
July 2010
November 2009
March 2009
November 2008
May 2008
October 2007
May 2007
March 2007
November 2006
May 2006
October 2005
May 2005
September 2004
May 2004
Release Date
Release Date
Table 6–4
lists revisions to the Nios II/s core.
No changes.
No changes.
No changes.
No changes.
No changes.
Implemented the illegal instruction exception.
Implemented the jmpi instruction.
No changes.
No changes.
No changes.
Cycle count for flushi and initi instructions changes from 1 to 4 cycles.
No changes.
Initial release of the Nios II/f core.
Added optional tightly-coupled memory ports. Designers can add zero to four
tightly-coupled instruction master ports.
Made instruction cache optional (previously instruction cache was always
present). If the instruction cache is not present, the Nios II core does not have an
instruction master port, and must use a tightly-coupled instruction memory.
Support for HardCopy devices (previous versions required a workaround to
support HardCopy devices).
Bug Fixes:
(1) When a store to memory is followed immediately in the pipeline by a load
from the same memory location, and the memory location is held in the data
cache, the load may return invalid data. This situation can occur in C code
compiled with optimization off (-O0).
(2) The SOPC Builder top-level system module included an extra, unnecessary
output port for systems with very small address spaces.
Notes
Notes
Nios II Processor Reference Handbook
6–5

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