IPR-NIOS Altera, IPR-NIOS Datasheet - Page 84

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–38
Nios II Processor Reference Handbook
1
Internal Interrupt Controller
When the internal interrupt controller is implemented, a peripheral device can
request a hardware interrupt by asserting one of the Nios II processor’s 32
interrupt-request inputs, irq0 through irq31. A hardware interrupt is generated if
and only if all three of these conditions are true:
■
■
■
Upon hardware interrupt, the processor clears the PIE bit to zero, disabling further
interrupts, and performs the other steps outlined in
page
The value of the ipending control register shows which interrupt requests (IRQ) are
pending. By peripheral design, an IRQ bit is guaranteed to remain asserted until the
processor explicitly responds to the peripheral.
between ipending, ienable, PIE, and the generation of an interrupt.
Although shadow register sets can be implemented in any Nios II/f processor, the
internal interrupt controller does not have features to take advantage of it as external
interrupt controllers do.
Figure 3–2. Relationship Between ienable, ipending, PIE and Hardware Interrupts
The PIE bit of the status control register is one.
An interrupt-request input, irqn, is asserted.
The corresponding bit n of the ienable control register is one.
3–43.
External hardware
interrupt request
inputs irq[31..0]
PIE bit
31
31
. . .
Generate
Hardware
ienable Register
Interrupt
ipending Register
Figure 3–2
. . .
. . .
“Exception Processing Flow” on
shows the relationship
December 2010 Altera Corporation
Chapter 3: Programming Model
Exception Processing
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