IPR-NIOS Altera, IPR-NIOS Datasheet - Page 39

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Processor Architecture
Memory and I/O Organization
December 2010 Altera Corporation
Memory Protection Unit
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For further details on the MMU implementation, refer to the
chapter of the Nios II Processor Reference Handbook.
You can optionally include the MMU when you instantiate the Nios II processor in
your Nios II hardware system. When present, the MMU is always enabled, and the
data and instruction caches are virtually-indexed, physically-tagged caches. Several
parameters are available, allowing you to optimize the MMU for your system needs.
For complete details of user-selectable parameters for the Nios II MMU, refer to the
Instantiating the Nios II Processor in SOPC Builder
Reference Handbook.
The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II
systems can include either an MMU or MPU, but cannot include both an MMU and
MPU on the same Nios II processor core.
The optional Nios II MPU provides the following features and functionality:
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32-bit virtual and physical addresses, mapping a 4-gigabyte (GB) virtual address
space into as much as 4 GB of physical memory
4 KB page and frame size
Low 512 megabytes (MB) of physical address space available for direct access
Hardware translation lookaside buffers (TLBs), accelerating address translation
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Format of page tables (or equivalent data structures) determined by system
software
Replacement policy for TLB entries determined by system software
Write policy for TLB entries determined by system software
Memory protection
Up to 32 instruction regions and 32 data regions
Variable instruction and data region sizes
Amount of region memory defined by size or upper address limit
Read and write access permissions for data regions
Execute access permissions for instruction regions
Overlapping regions
Separate TLBs for instruction and data accesses
Read, write, and execute permissions controlled per page
Default caching behavior controlled per page
TLBs acting as n-way set-associative caches for software page tables
TLB sizes and associativities configurable at system generation
chapter of the Nios II Processor
Nios II Processor Reference Handbook
Programming Model
2–17