IPR-NIOS Altera, IPR-NIOS Datasheet - Page 47

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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NII51003-10.1.0
Introduction
Operating Modes
Nios II Processor Reference Handbook
December 2010
December 2010
NII51003-10.1.0
f
1
This chapter describes the Nios
at the assembly language level. Fully understanding the contents of this chapter
requires prior knowledge of computer architecture, operating systems, virtual
memory and memory management, software processes and process management,
exception handling, and instruction sets. This chapter assumes you have a detailed
understanding of the aforementioned concepts and focuses on how these concepts are
specifically implemented in the Nios II processor. Where possible, this chapter uses
industry-standard terminology.
This chapter discusses the following topics from the system programmer’s
perspective:
■
■
■
■
■
■
■
■
Because of the flexibility and capability range of the Nios II processor, this chapter
covers topics that support a variety of operating systems and runtime environments.
While reading, be aware that all sections might not apply to you. For example, if you
are using a minimal system runtime environment, you can skip the sections covering
operating modes, the MMU, the MPU, or the control registers exclusively used by the
MMU and MPU.
High-level software development tools are not discussed here. Refer to the
Software Developer’s Handbook
Operating modes control how the processor operates, manages system memory, and
accesses peripherals. The Nios II architecture supports these operating modes:
Operating modes,
and memory.
Memory management unit (MMU),
for full-featured operating systems.
Memory protection unit (MPU),
virtual memory management.
Registers,
Working With the MPU,
and operation.
Exception processing,
to exceptions.
Memory and Peripheral Access,
Instruction set categories,
page
3–10—Describes the Nios II register sets.
page
page
3–1—Defines the relationships between executable code
page
page
for information about developing software.
3–30—Describes how the Nios II processor responds
®
II programming model, covering processor features
3–29—Provides an overview of MPU initialization
3–55—Introduces the Nios II instruction set.
page
page
page
3–53—Describes Nios II addressing.
3–8—Describes memory protection without
3–3—Describes virtual memory support
3. Programming Model
Nios II
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