IPR-NIOS Altera, IPR-NIOS Datasheet - Page 58

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–12
Table 3–7. status Control Register Fields
Table 3–8. status Control Register Field Descriptions (Part 1 of 3)
Nios II Processor Reference Handbook
31
RSIE
NMI
Bit
30
29
Reserved
RSIE is the register set interrupt-enable bit. When set to 1, this bit allows
the processor to service external interrupts requesting the register set that
is currently in use. When set to 0, this bit disallows servicing of such
interrupts.
NMI is the nonmaskable interrupt mode bit. The processor sets NMI to 1
when it takes a nonmaskable interrupt.
28
27
26
Table 3–6. Control Register Names and Bits (Part 2 of 2)
The following sections describe the nonreserved control registers.
The status Register
The value in the status register determines the state of the Nios II processor. All
status bits are set to predefined values at processor reset. Some bits are exclusively
used by and available only to certain features of the processor, such as the MMU,
MPU or external interrupt controller (EIC) interface.
status register.
Table 3–8
25
8
9
10
11
12
13
14
15
16–31
Notes to
(1) Available only when the MMU is present. Otherwise reserved.
(2) Available only when the MPU is present. Otherwise reserved.
(3) Available only when the external interrupt controller interface is not present. Otherwise reserved.
Register
24
23
Table
gives details of the fields defined in the status register.
22
pteaddr
tlbacc
tlbmisc
Reserved
badaddr
config
mpubase
mpuacc
Reserved
3–6:
21
Description
20
Name
(1)
(2)
(2)
19
(1)
(1)
(2)
PRS
18
17
Refer to
Refer to
Refer to
Reserved
Refer to
Refer to
Refer to
Refer to
Reserved
16
15
Table 3–13 on page 3–16
Table 3–15 on page 3–17
Table 3–17 on page 3–18
Table 3–19 on page 3–21
Table 3–21 on page 3–21
Table 3–23 on page 3–22
Table 3–25 on page 3–23
14
13
CRS
12
11
Register Contents
10
Table 3–7
9
Read/Write
Access
8
Read
December 2010 Altera Corporation
7
IL
Chapter 3: Programming Model
shows the layout of the
6
5
Reset
1
0
4
3
and shadow
Available
sets only
interface
interface
only
register
2
EIC
EIC
(4)
Registers
U
1
(3)
0