IPR-NIOS Altera, IPR-NIOS Datasheet - Page 285

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
trap
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
0
28
27
26
25
24
0
estatus ← status
PIE ← 0
U ← 0
ea ← PC + 4
PC ← exception handler address
trap
trap imm5
trap
Saves the address of the next instruction in register ea, saves the contents of the status
register in estatus, disables interrupts, and transfers execution to the exception handler. The
address of the exception handler is specified at system generation time.
The 5-bit immediate field imm5 is ignored by the processor, but it can be used by the debugger.
trap with no argument is the same as trap 0.
To return from the exception handler, execute an eret instruction.
Trap
R
IMM5 = Type of breakpoint
23
22
21
20
0x1d
19
18
17
16
15
14
0x2d
13
12
11
10
9
IMM5
8
Nios II Processor Reference Handbook
7
6
5
4
0x3a
3
2
1
trap
8–99
0