IPR-NIOS Altera, IPR-NIOS Datasheet - Page 160

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–4
Table 6–3. Nios II/f Core Revisions (Part 2 of 3)
Nios II Processor Reference Handbook
8.0
7.2
7.1
7.0
6.1
6.0
5.1 SP1
5.1
5.0
1.1
Version
May 2008
October 2007
May 2007
March 2007
November 2006
May 2006
January 2006
October 2005
May 2005
December 2004
Release Date
■
■
■
■
Implemented the jmpi instruction.
No changes.
No changes.
No changes.
Cycle count for flushi and initi instructions changes from 1 to 4 cycles.
Bug Fix:
Back-to-back store instructions can cause memory corruption to the stored data.
If the first store is not to the last word of a cache line and the second store is to the
last word of the line, memory corruption occurs.
No changes.
■
■
■
■
■
■
■
Implemented the optional MMU.
Implemented the optional MPU.
Implemented advanced exception checking.
Implemented the initda instruction.
Added optional tightly-coupled memory ports. Designers can add zero to four
tightly-coupled instruction master ports, and zero to four tightly-coupled data
master ports.
Made the data cache line size configurable. Designers can configure the data
cache with the following line sizes: 4, 16, or 32 bytes. Previously, the data
cache line size was fixed at 4 bytes.
Made instruction and data caches optional (previously, cache memories were
always present). If the instruction cache is not present, the Nios II core does
not have an instruction master port, and must use a tightly-coupled instruction
memory.
Support for HardCopy devices (previous versions required a workaround to
support HardCopy devices).
Added user-configurable options affecting multiply and shift operations. Now
designers can choose one of three options:
(1) Use embedded multiplier resources available in the target device family
(previously available).
(2) Use logic elements to implement multiply and shift hardware (new option).
(3) Omit multiply hardware. Shift operations take one cycle per bit shifted;
multiply operations are emulated in software (new option).
Added cpuid control register.
Bug Fix:
Interrupts that were disabled by wrctl ienable remained enabled for one
clock cycle following the wrctl instruction. Now the instruction following such
a wrctl cannot be interrupted.
Notes
Chapter 6: Nios II Processor Revision History
December 2010 Altera Corporation
Core Revisions