IPR-NIOS Altera, IPR-NIOS Datasheet - Page 259

• Manufacturer Part Number: IPR-NIOS
• Description: IP NIOS II MEGACORE RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-NIOS

• License: Renewal License
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Instruction Set Reference
Instruction Set Reference
mulxsu
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
B
rC ← ((signed) rA) × ((unsigned) rB))
mulxsu rC, rA, rB
mulxsu r6, r7, r8
Treating rA as a signed integer and rB as an unsigned integer, mulxsu multiplies rA times rB,
and stores the 32 high-order bits of the product to rC.
Nios II processors that do not implement the mulxsu instruction cause an unimplemented
instruction exception.
mulxsu can be used as part of the calculation of a 128-bit product of two 64-bit signed
integers. Given two 64-bit integers, each contained in a pair of 32-bit registers, (S1 : U1) and
(S2 : U2), their 128-bit product is: (U1 × U2) + ((S1 × U2) << 32) + ((U1 × S2) << 32) + ((S1 ×
S2) << 64). The mulxsu and mul instructions are used to calculate the two 64-bit products S1
× U2 and U1 × S2.
Unimplemented instruction
R
A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
23
22
21
20
19
C
18
17
16
15
14
0x17
63..32
13
multiply extended signed/unsigned
12
11
10
9
0
8
Nios II Processor Reference Handbook
7
6
5
4
0x3a
3
2
1
8–73
0