DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 245

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Generating a Timing-annotated Netlist
Basic Timing Simulation Process
Note: Naming the nets during your design entry is very important
for both functional and timing simulation. This allows you to find the
nets in the simulations more easily than looking for a machine-gener-
ated name
Before performing timing simulation on your design, you must
generate a timing-annotated netlist by implementing the design as
follows.
1.
2.
3.
4.
After the design has been implemented and timing simulation data
produced as described in“Generating a Timing-annotated Netlist”
section, you can perform a timing simulation. This section describes
the basic steps to perform timing simulation.
1.
Within the Project Manager, click the Implementation icon.
a) For Schematic Flow projects, this opens the Implement
b) For HDL Flow projects, this opens the Synthesis/Implemen-
Click the Options button. This opens the Options dialog box.
Verify that the Simulation Template is Foundation EDIF.
(Change it to Foundation EDIF, if necessary.)
Implement the design.
a) For Schematic Flow projects, click Run in the Implement
b) For HDL Flow projects, click OK in the Synthesis/Implemen-
Open the Timing Simulator by clicking the Timing Simulation
icon on the Verification phase button.
Design dialog box.
tation dialog box.
Design dialog box.
tation dialog box.
Verification and Programming
12-3