DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 161

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Synthesis of HDL Modules
Schematic Flow Methodology
Figure 6-3 CORE Generator Templates in Language Assistant
Foundation projects can be either Schematic Flow or HDL Flow
projects. Many of the HDL editing and synthesis operations
described in this section are the same for both flows; however, differ-
ences do exist and are noted where appropriate. This section
describes how to synthesize your design without also continuing
through implementation.
In a Schematic Flow project, VHDL and Verilog modules can only be
underlying modules in a top-level schematic design. Each HDL file is
synthesized and optimized separately. Top-level ABEL designs and
ABEL State Machine designs are only supported in the Schematic
Flow.
The Schematic Flow methodology can be beneficial if you have a few
HDL blocks in an otherwise schematic environment. In this case, you
synthesize each individual HDL module separately.
Following is the general procedure to synthesize HDL Modules in
Schematic Flow Projects.
1.
Open the HDL file in the HDL Editor. This can be done by the
methods listed in the “HDL File Selection” section or by double
HDL Design Entry and Synthesis
6-5