DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 279

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
The following file corresponds to the preceding figure.
The first line of the above example illustrates the application of the
TNM (Timing Name) PIPEA to the net named DATA_EN. The second
line illustrates the TIMEGRP design object formed using a pattern
matching mechanism in conjunction with the predefined TIMEGRP
“PADS”. In this example, the TIMEGRP named BUSPADS will
include only those PADs with names that start with BUS.
Each of the user-defined Timegroups is then used to define the object
space constrained by the timing specification (Timespec) named
TS01. This timing specification states that all paths from each member
of the BUSPADS group to each member of the PIPEA group need to
have a path delay that does not exceed 20 nanoseconds (ns are the
default units for time). The TIMESPEC TS02 constraint illustrates a
similar type of timing constraint using the predefined groups FFS
and RAMS.
# This is a comment line
# UCF FROM:TO style Timespecs
# Spaces or colons (:) may be used as field separators
BUS0
BUS1
B3
B4
NET DATA_EN TNM = PIPEA ;
TIMEGRP BUSPADS = PADS(BUS*) ;
TIMESPEC TS01 = FROM:BUSPADS:TO:PIPEA:20 ;
TIMESPEC TS02 = FROM FFS TO RAMS 15 ;
BUSPADS=PADS(BUS*)
TIMESPEC
DATA_EN
TNM=PIPEA
TS01=FROM:BUSPADS:TO:PIPEA:20
TS02=FROM FFS TO RAMS 15
TIMESPEC
Foundation Constraints
D
EN
D
EN
Q
Q
X8572
Q1
Q2
B-7