DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 54

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
2-22
an FPGA implementation revision. For more information on the
Floorplanner, see the Floorplanner Guide, an online book.
FPGA Editor
Selecting Tools
Project Manager window opens the FPGA Editor. The FPGA Editor
provides a graphic view of your placed and routed design, allowing
you to make modifications. This option is supported for FPGAs only.
For more information on using the FPGA Editor, see the FPGA Editor
Guide, an online book.
CPLD ChipViewer
Selecting Tools
the Project Manager window opens the ChipViewer. The ChipViewer
provides a graphical view of the CPLD fitting report. With this tool
you can examine inputs and outputs, macrocell details, equations,
and pin assignments. You can examine both pre-fitting and post-
fitting results.
More information on using the CPLD ChipViewer is available in that
tool’s online help or from the Umbrella Help menu accessed by Help
Viewer.
Automatic Pin Locking
I/O pins can be locked to a previous revision by clicking on the revi-
sion in the Versions tab of the Project Manger and selecting Tools
Implementation
dialog appears upon completion. You can click View Lock Pins
Report from the Lock Pin Status dialog or select Tools
mentation
Report. The Lock Pins Report contains information on any constraint
conflicts between the pin locking constraints in the existing UCF file
and the design file.
Foundation Help Contents
View Locked Pins Report to access the Lock Pins
Implementation
Implementation
Lock Device Pins. The Lock Pins Status
Advanced Tools
FPGA Editor from the
CPLD ChipViewer from
Xilinx Development System
Chip-
Imple-