DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 244

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Timing Simulation
12-2
•
When the design meets your requirements, the last step in its
processing is downloading the design and programming the target
device.
Timing simulation verifies that your design runs at the desired speed
for your device under worst-case conditions. It can verify timing rela-
tionships and determine the critical paths for the design under worst-
case conditions. It can also determine whether the design contains
set-up or hold violations.
The procedures for functional and timing simulation are nearly iden-
tical. Functional simulation is performed before the design is placed
and routed and simulates only the functionality of the logic in the
design. Timing simulation is performed after the design is placed and
routed and uses timing information based on the delays in the placed
and routed design. Timing simulation describes the circuit behavior
far more accurately than Functional simulation.
Like functional simulation, you must use input stimulus to run the
simulation. To create stimulus, refer to the“Functional Simulation”
chapter.
•
•
In-circuit verification
As a final test, you can verify how your design performs in the
target application. In-circuit verification tests the circuit under
typical operating conditions. To perform in-circuit verification,
you download your design bitstream into a device with the
Xilinx XChecker cable. Refer to “In-Circuit Verification” in the
Device Programming section of this chapter for information.
For Foundation Express users, the Express Time Tracker
provides post-synthesis, pre-implementation timing analysis
for HDL Flow projects. Refer to “Express Time Tracker”
section of the “Design Methodologies - HDL Flow” chapter
for information.
For Schematic Flow projects and HDL Flow projects, static
timing analysis can be done at two different stages of the
Implementation phase for FPGA devices: after Map or after
Place and Route. It can be done after Fit for CPLDs. Refer to
the “Timing Analyzer” section in this chapter for information
on static timing analysis within the Implementation phase.
Xilinx Development System