DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 21

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Chapter 3
Foundation Series 2.1i User Guide
Device Programming...................................................................... 2-23
Utilities............................................................................................ 2-24
Design Methodologies - Schematic Flow
Schematic Flow Processing Overview ........................................... 3-1
Top-Level Designs ......................................................................... 3-3
All-Schematic Designs ................................................................... 3-3
Schematic Designs with Instantiated HDL-Based Macros ............. 3-13
Schematic Designs With Instantiated LogiBLOX Modules............. 3-15
Schematic Designs With Instantiated CORE Generator Cores ..... 3-16
Schematic Designs With Finite State Machine (FSM) Macros....... 3-18
Finite State Machine (FSM) Designs ............................................. 3-20
JTAG Programmer.................................................................... 2-23
PROM File Formatter................................................................ 2-23
Hardware Debugger.................................................................. 2-23
Schematic Symbol Library Manager ......................................... 2-24
Command History ..................................................................... 2-24
Project Notes ............................................................................ 2-25
Implementation Template Manager .......................................... 2-25
ABEL to VHDL/Verilog Converter ............................................. 2-25
Altera HDL to VHDL/Verilog Converter..................................... 2-25
Creating the Schematic and Generating a Netlist..................... 3-3
Performing Functional Simulation ............................................. 3-4
Implementing the Design .......................................................... 3-5
Editing Implementation Constraints .......................................... 3-8
Verifying the Design.................................................................. 3-11
Programming the Device .......................................................... 3-12
Creating HDL Macros ............................................................... 3-13
Creating the Schematic and Generating a Netlist..................... 3-14
Creating LogiBLOX Modules .................................................... 3-15
Importing Existing LogiBLOX Modules ..................................... 3-15
Creating Core Symbols............................................................. 3-16
Creating FSM Macros ............................................................... 3-18
Creating the Schematic and Generating a Netlist..................... 3-19
Creating a State Editor Design ................................................. 3-20
FPGA Editor......................................................................... 2-22
CPLD ChipViewer................................................................ 2-22
Automatic Pin Locking ......................................................... 2-22
Creating a New Revision ..................................................... 3-7
Creating a New Version....................................................... 3-8
Performing a Static Timing Analysis (Optional) ................... 3-11
Performing a Timing Simulation........................................... 3-11
Contents
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