DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 268

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
state diagram
state machine
state machine designs
states
static timing analysis
static timing analyzer
A-16
A state diagram is a pictorial description of the outputs and required
inputs for each state transition as well as the sequencing between
states. Each circle in a state diagram contains the name of a state.
Arrows to and from the circles show the transitions between states
and the input conditions that cause state transitions. These conditions
are written next to each arrow.
A state machine is a set of combinatorial and sequential logic
elements arranged to operate in a predefined sequence in response to
specified inputs. The hardware implementation of a state machine
design is a set of storage registers (flip-flops) and combinatorial logic,
or gates. The storage registers store the current state, and the logic
network performs the operations to determine the next state.
State machine designs typically start with the translation of a concept
into a “paper design,” usually in the form of a state diagram or a
bubble diagram. The paper design is converted to a state table and,
finally, into the source code itself.
The values stored in the memory elements of a device (flip-flops,
RAMs, CLB outputs, and IOBs) that represent the state of that device
for a particular readback (time). To each state, there corresponds a
specific set of logical values.
A static timing analysis is a point-to-point delay analysis of a design
network.
A static timing analyzer is a tool that analyzes the timing of the
design on the basis of its paths.
Xilinx Development System