DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 144

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
5-42
9.
10. Open a second session of the HDL Editor. In the second HDL
Note: Instead of opening a second sesssion, you could use Edit
Insert File from the HDL Editor tool bar to insert the file into the
current HDL Editor session.
11. Cut and paste the Component Declaration from the CORE
12. Check the syntax of the VHDL design code by selecting
13. The design with the instantiated CORE module can then be
Note: When the design is synthesized, a warning is generated that
the CORE module is unexpanded. Modules instantiated as black
boxes are not elaborated and optimized. The warning message is just
reflecting the black box instantiation.
14. To complete the design, refer to the “Synthesizing the
Note: The instantiated module must be in the same directory as the
HDL code in which it is instantiated.
Verilog Instantiation
This section explains how to instantiate a CORE component into a
Verilog design using Foundation.
In the HDL Editor, open the CORE’s .vho file
(component_name.vho) located under the current project.
Editor window, open the VHDL file in which the CORE compo-
nent is to be instantiated.
component’s .vho file to your project’s VHDL code, placing it
after the architecture statement in the VHDL code.
Cut and past the Component Instantiation from the CORE
component’s .vho file to your VHDL design code after the
“begin” line. Give the inserted code an instance name. Edit the
code to connect the signals in the design to the ports of the CORE
component.
Synthesis
errors. Then save the design and close the HDL Editor.
synthesized (click the Synthesis button on the Flow tab).
Design”through the “Programming the Device” sections under
the “All-HDL Designs” section.
Check Syntax in the HDL Editor. Correct any
Xilinx Development System