DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 304

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
---User Constraint File (UCF):
# This is a comment
# Period specifies minimum PERIOD of CLK net. Offset specifies that
# data on MAY can arrive up to 6 ns before the clock edge arrives on CLK.
# NOTE: Period constraints do not apply to elements in input or output
pads.
NET CLK PERIOD = 20 ns ;
NET MAY OFFSET = IN 6ns before CLK_PD ;
# Groups all clocked loads of CLK2 into CLK2_LOADS timegroup
# Groups all clocked loads of VAL into VAL_LOADS
# timegroup TNM # => Timegroup NaMe
NET CLK2 TNM=CLK2_LOADS ;
NET VAL TNM=VAL_LOAD ;
# Specifies worst case speed of path from IPAD to CLK2 # loads. Includes
# pad, buffer, and net delays. TS0l is a Timespec identifier; it can
# have names of the form TS<string>. PADS (CLK2_PD) is a Timegroup name
# specified inside of a Timespec.
TIMESPEC TS01=FROM PADS (CLK2_PD) TO CLK2_LOADS=15ns ;
# Specifies the maximum frequency for all loads clocked by CLK2.
TIMESPEC TS02=FROM CLK2_LOADS TO CLK2_LOADS=30Mhz;
# Specifies the minimum delay on the path from Synchronous RAM to OFD.
# Includes clock-to-out“User Constraint File Example” delay, net delay,
and setup time.
TIMESPEC TS03=FROM CLK2_LOADS TO VAL_LOAD=15000ps ;
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