DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 288

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Layout Constraints
B-16
Converting a Logical Design to a Physical Design
•
Layout constraints also have an inherent precedence which is based
on the type of constraint and the site description provided to the
tools. If two constraints have the same priority and cover the same
path, then the last constraint in the constraint file will override any
other constraints that overlap.
(FPGA only.) The mapping constraints in the example below illus-
trate some of the capabilities to control the implementation process
for a design. The OPTIMIZE attribute is attached to the block of logic
associated with the instance “GLUE.”All of the combinatorial logic
within the block GLUE will be optimized for speed (minimizing
levels of logic) while other aspects of the design will be processed by
the default mapping algorithms (assuming the design-based optimi-
zation switches are not issued).
The layout constraint in the example above illustrates the use of a full
hierarchical path name for the net named DATA0_IN in the
application of the I/O location constraint. In this example, IOBLOCK
is a hierarchical boundary that contains the net DATA0_IN. Location
constraints applied to “pad nets” are used to constrain the location of
the PAD itself, in this case to site P12.
Note: If the design contains a PAD, the constraint could have been
just as easily applied to it directly (some design flows do not provide
explicit I/O pads in the design netlist).
The process of mapping translates a design from the logical design
domain to the physical design domain. The MAP process creates both
the physical design components (CLBs, IOBs, and so forth) and the
physical design constraints (layout and timing). The physical design
components are written into a Native Circuit Description (NCD) file.
“Allpaths” type constraints—the lowest priority
# Mapping constraint
INST GLUE OPTIMIZE = SPEED ;
# Layout constraint
NET IOBLOCK/DATA0_IN LOC = P12 ;
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