DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 147

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
/*******************************************************************
* This file was created by the Xilinx CORE Generator tool, and
* is (c) Xilinx, Inc. 1998, 1999. No part of this file may be
* transmitted to any third party (other than intended by Xilinx)
* or used without a Xilinx programmable or hardwire device without *
* Xilinx’s prior written permission.
*******************************************************************/
// The following line must appear at the top of the file in which
// the core instantiation will be made. Ensure that the translate_off/_on
// compiler directives are correct for your synthesis tool(s)
//----------- Begin Cut here for LIBRARY inclusion --------// LIB_TAG
// synopsys translate_off
‘include "XilinxCoreLib/C_MEM_SP_BLOCK_V1_0.v"
// synopsys translate_on
// LIB_TAG_END ------- End LIBRARY inclusion --------------
The component name is the name given to the CORE in the
customization window. The port names are the names provided
in the .veo file.
An example .veo file produced by the CORE Generator system
follows.
component_name.coe
component_name.xco
component_name.edn
component_name.veo
component_name.mif
ASCII data file defining the coeffi-
cient values for FIR filters and
initialization values for memory
modules
CORE Generator file containing the
parameters used to generate the
customized CORE
EDIF implementation netlist for the
CORE
Verilog template file
Memory Initialization Module for
Virtex Block RAM modules
Design Methodologies - HDL Flow
*
*
*
*
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