DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 308

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DS-FND-BSX-PC

Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet

Specifications of DS-FND-BSX-PC

For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
Foundation Series 2.1i User Guide
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity test is
architecture details of test is
signal dataoutreg,datareg: STD_LOGIC_VECTOR(1 downto 0);
signal addrreg: STD_LOGIC_VECTOR(4 downto 0);
component inside
B-36
port(
end test;
port(
DATA: in STD_LOGIC_VECTOR(1 downto 0);
DATAOUT: out STD_LOGIC_VECTOR(1 downto 0);
ADDR: in STD_LOGIC_VECTOR(4 downto 0);
C, ENB: in STD_LOGIC);
MDATA: in STD_LOGIC_VECTOR(1 downto 0);
MDATAOUT: out STD_LOGIC_VECTOR(1 downto 0);
MADDR: in STD_LOGIC_VECTOR(4 downto 0);
HDL Flow VHDL Example
inside.v:
test.ucf
Following is a VHDL example.
test.vhd
module inside(MDATA,MDATAOUT,MADDR,C,WE);
input [1:0] MDATA;
output [1:0] MDATAOUT;
input [4:0] MADDR;
input C;
input WE;
memory U0 ( .A(MADDR), .DO(MDATAOUT),
endmodule
INST “U0_U0” TNM = usermem;
TIMESPEC TS_6= FROM : FFS :TO: usermem: 50;
INST “U0_U0/mem0_0” LOC=CLB_R7C2;
.DI(MDATA), .WR_EN(WE), .WR_CLK(C));
Xilinx Development System

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