DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 231

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
CPLD Fitter
•
For a complete description of PAR, see the “PAR—Place and Route”
chapter in the Development System Reference Guide.
The CPLD Fitter implements designs for the XC9500/XL devices. The
Fitter outputs the files listed below.
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For detailed information about implementing CPLD designs, refer to
the CPLD Design Techniques and CPLD Flow Tutorial in the Foundation
on-line help.
Timing-Driven — PAR places and routes a design based upon
your timing constraints.
The Fitting report (design_name.rpt) lists a summary and detailed
information about the logic and I/O pin resources used by the
design, including the pinout, error and warning messages, and
Boolean equations representing the implemented logic.
The Static timing report (design_name.tim) shows a summary
report of worst-case timing for all paths in the design; it
optionally includes a complete listing of all delays on each
individual path in the design.
The Guide file (design_name.gyd) contains all resulting pinout
information required to reproduce the current pinout if you run
the Lock Pins command before the next time the fitter is run for
the same design. (The Guide file is written only upon successful
completion of the fitter.) Multi-Pass Place and Route and Guide
Files are not accessible via the Foundation Project Manager.
Access these functions through the standalone Design Manager
(Start
The Programming file (design_name.jed for XC9000) is a JEDEC-
formatted (9k) programming file to be downloaded into the
CPLD device.
Timing simulation database (design_name.nga) is a binary
database representing the implemented logic of the design,
including all delays, consisting of Xilinx simulation model
primitives (simprims).
Programs
Accessories
Design Implementation
Design Manager.
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