DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 286

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
B-14
Controlling Skew
Constraint Precedence
On the other hand, the following syntax indicates that the layout
tools should ignore paths through the
known Timespecs.
(FPGA only.) Skew is the difference between the minimum and
maximum of the maximum load delays on a net. You can control the
maximum allowable skew on a net by attaching the MAXSKEW
attribute directly to the net.
The above example indicates that 3 ns is the maximum skew allowed
on
see the “Additional Timing Constraints” section in the Development
System Reference Guide.
A design may assign a precedence to Timespecs only within a certain
class of constraints. For example, you may specify a priority for a
particular From:To specification to be greater than another, but you
may not specify a From:To constraint to have priority over a TIG
constraint. The following example illustrates the explicit assignment
of priorities between two same-class timing constraints, the lowest
number having the highest priority.
The following sections illustrate the order of precedence for the
various types (and various sources) of timing constraints.
$1I345/net_a
#Global TIG example (UCF file)
#MAXSKEW example (UCF file)
# Priority UCF example
NET $1I456/slow_net TIG=TS01, TS04 ;
NET $1I456/slow_net TIG
NET $1I345/net_a MAXSKEW=3 ;
TIMESPEC TS01 = FROM GROUPA TO GROUPB 40 PRIORITY 4;
TIMESPEC TS02 = FROM GROUP1 TO GROUP2 35 PRIORITY 2;
. For a detailed example of how MAXSKEW works,
$1I456/slow_net
Xilinx Development System
net for all