DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 290

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Efficient Use of Timespecs and Layout Constraints
B-18
The “Starter Set” of Timing Constraints
•
The previous section described the mechanisms available for
constraining a design’s timing within the Foundation tools. The
sections that follow summarize each of the constraints that are
available.
The robust nature of the language enables you to define your design
requirements at the highest level of abstraction first, and then fine
tune the timing requirements by using more specific Timespecs, if
needed. This is the methodology that will best describe your require-
ments to the tools.
The following observations help to illustrate the reasons why this
methodology should be followed (from a tool runtime perspective).
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•
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In conclusion, overall design runtime is improved when a “qualified
global” timing methodology is employed instead of a “thorough-
detailed” timing methodology.
The following examples clearly identify the “preferred” mechanism
for controlling the timing of your design. The preferred method
assumes a goal of getting the required results in the fastest run time
possible. If the design has a single clock and required I/O timing that
The XC5200XL family does not have flip-flops in the IOB, so two
new constraints have been provided: INREG and OUTREG. PAR
will attempt to place a register with a INREG attribute near the
IOB that drives its Din pin, so it can use fast routes. OUTREG will
cause PAR to attempt to place a register near the IOB that Qout
sources, as shown in the following example.
INST near_input_flop INREG ;
INST near_output_flop OUTREG ;
Using explicit Timegroups causes slower runtimes than using
implicit timegroups arising from the use of constraints such as
PERIOD.
Processing larger Timegroups takes longer than processing
smaller Timegroups.
Using many specific Timespecs results in slower runtimes than
using a smaller set of more general Timespecs.
Xilinx Development System