DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 133

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
8.
9.
Note: When the design is synthesized, a warning is generated that
the LogiBLOX module is unlinked. Modules instantiated as black
boxes are not elaborated and optimized. The warning message is just
reflecting the black box instantiation.
10. To complete the design, refer to the “Synthesizing the
Verilog Instantiation
This section explains how to instantiate a LogiBLOX module into a
Verilog design using Foundation. The example described below
creates a RAM48X4S using LogiBLOX.
1.
2.
3.
begin
UO:userff port map (D=>D, CE=>CE, CLK=>CLK, Q=>Q);
U1:memory port map(A=>Atop,DI=>DItop,WR_EN=>WR_ENtop,
end inside;
Check the syntax of the VHDL design code by selecting
Synthesis
errors. Then save the design and close the HDL Editor.
The design with the instantiated LogiBLOX module can then be
synthesized (click the Synthesis button on the Flow tab).
Design”through the “Programming the Device” sections under
the “All-HDL Designs” section.
Access the LogiBLOX Module Selector window using one of the
following methods. Its operation is the same regardless of where
it is invoked.
•
•
•
Click Setup on the LogiBLOX Module Selector screen. (The first
time LogiBLOX is invoked, the Setup screen appears automati-
cally.)
In the Setup window, enter the following items.
From the Project Manger, select Tools
LogiBLOX module generator.
From the HDL Editor, select Tools
From Schematic Editor, select Tools
Generator.
Check Syntax in the HDL Editor. Correct any
WR_CLK=>WR_CLKtop, DO=>DOtop);
Design Methodologies - HDL Flow
LogiBLOX.
LogiBLOX Module
Design Entry
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