DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 149

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
.CLK(CLK),
.DI(DI),
.WE(WE),
.EN(EN),
.RST(RST),
.DO(DO));
// synopsys translate_on
endmodule
// MOD_TAG_END ------- End MODULE Declaration -------------
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
mux4 YourInstanceName (
.ADDR(ADDR),
.CLK(CLK),
.DI(DI),
.WE(WE),
.EN(EN),
.RST(RST),
.DO(DO));
// INST_TAG_END ------ End INSTANTIATION Template ---------
8.
9.
10. Open a second session of the HDL Editor. In the second HDL
Note: Instead of opening a second sesssion, you could use Edit
Insert File from the HDL Editor tool bar to insert the file into the
current HDL Editor session.
11. Cut and paste the Component Declaration from the CORE
Select File
In the HDL Editor, open the CORE’s .veo file
(component_name.veo) located under the current project.
Editor window, open the Verilog file in which the CORE compo-
nent is to be instantiated.
component’s .veo file to your project’s Verilog code, placing it
after the architecture statement in the Verilog code.
Cut and past the Component Instantiation from the CORE
component’s .veo file to your Verilog design code after the
Exit to close the CORE Generator.
Design Methodologies - HDL Flow
5-47