DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 69

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Verifying the Design
6.
Performing a Static Timing Analysis (Optional)
1.
2.
For FPGAs, you can perform a post-MAP or post-place timing
analysis to obtain rough timing information before routing delays are
added. You can also perform a post-implementation timing analysis
on CPLDs after a design has been implemented using the CPLD fitter.
For details on how to use the Timing Analyzer, select Help
dation Help Contents
Performing a Timing Simulation
1.
Click the Implementation icon on the Project Manager’s Flow tab
to rerun Translate (and the other phases).
Or, to just rerun the Translate phase, select Tools
tation
phase when prompted. Then click the Step button at the bottom
of the Flow Engine Window window. Exit the Flow Engine when
the Translate phase is Completed.
Click the Timing Analyzer icon in the Verification box on the
Project Manager’s Flow tab.
Perform a static timing analysis on mapped or placed and routed
designs for FPGAs.
Open the Timing Simulator by clicking the Timing Simulation
icon in the Verification box on the Project Managers’s Flow tab.
The implementation timing netlist will be loaded into the simu-
lator.
Flow Engine. Click Yes to start at the Translate
Timing Analyzer.
Design Methodologies - Schematic Flow
Implemen-
Foun-
3-11