DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 285
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DS-FND-BSX-PC
Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet
1.DS-FND-BSX-PC.pdf
(330 pages)
Specifications of DS-FND-BSX-PC
For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
- Current page: 285 of 330
- Download datasheet (3Mb)
Foundation Series 2.1i User Guide
Ignoring Paths
This same timing constraint could be applied using the
FROM:PADS:TO:FFS timing constraint. However, using a From:To
methodology would require you to know the intrinsic CLK net delay,
and you would have to adjust the value assigned to the From:To
Timespec. The internal CLK net delay is implicit in the OFFSET/
PERIOD constraint. Furthermore, migrating the design to another
speed grade or device would require modification of the From:To
Timespec to accommodate the new intrinsic CLK net delay. An alter-
native solution is to use the flip-flop in the IOB of certain FPGA archi-
tectures (XC4000E/EX, for instance), as the clock-to-setup time is
specified in the Programmable Logic Data Book.
Note: Relative Timespecs can only be applied to similar Timespecs.
For example, a PERIOD Timespec may be defined in terms of another
PERIOD Timespec, but not a FROM:TO Timespec.
(FPGA only.) When you declare a a Timespec that includes paths
where the timing is not important, the tools may create a less optimal
route since there is more competition for routing resources. This
problem can be alleviated by using a TIG (timing ignore) attribute on
the non-critical nets. TIG causes all paths that fan out from the net or
pin where it is applied to be “ignored” during timing simulation.
You can create a Timing Ignore constraint with the Constraints Editor.
The following syntax indicates that
have the Timespec TS01 or TS04 applied to it.
with respect to CLK
OFFSET of ADD0
#Timespec-specific TIG example (UCF file)
IOB
CLK IOB
ADD0 IN
CLK IN
$1I456/slow_net
ADD0
Foundation Constraints
CLK
p/o CLB
should not
D Q
X8086
B-13
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