DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 61

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
Top-Level Designs
All-Schematic Designs
Creating the Schematic and Generating a Netlist
Schematic Flow projects can have top-level schematic or Finite State
Machine (ABEL) designs. A top-level design can have any number of
underlying schematic, HDL, LogiBLOX, CORE Generator, ABEL, or
Finite State Machine (FSM) macros. Although individual modules
may require some form of synthesis, the entire project is not
synthesized and the netlist that is exported for implementation is not
optimized across module boundaries as in an HDL Flow project.
The following procedure describes how to create a top-level sche-
matic design that contains schematics only, that is, there are no
instantiated HDL or State Machine macros.
This section lists the basic steps for creating a schematic and gener-
ating a netlist from it.
1.
2.
3.
4.
For more information about schematic designs, see the “Schematic
Design Entry” chapter or in the Schematic Editor window, select
Help
Open the Schematic Editor by selecting the Schematic Editor icon
from the Design Entry box on the Project Manager’s Flow tab.
Select Mode
schematic. Select specific components from the SC Symbols
window.
Complete your schematic by placing additional components
from the Symbol toolbox including I/O ports, nets, buses, labels,
and attributes.
Save your schematic by selecting File
Schematic Editor Help Contents.
Symbols to add components to your new
Design Methodologies - Schematic Flow
Save.
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