DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 141

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
----------------------------------------------------------------------
-- This file was created by the Xilinx CORE Generator tool, and
-- is (c) Xilinx, Inc. 1998, 1999. No part of this file may be
-- transmitted to any third party (other than intended by Xilinx)
-- or used without a Xilinx programmable or hardwire device without --
-- Xilinx’s prior written permission.
----------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component sram
port (
addr: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
di: IN std_logic_VECTOR(3 downto 0);
we: IN std_logic;
en: IN std_logic;
rst: IN std_logic;
do: OUT std_logic_VECTOR(3 downto 0));
end component;
The customized CORE component is a collection of several files
including those listed below. The files are located in your Xilinx
project directory for the current project.
The component name is the name given to the CORE in the
customization window. The port names are the names provided
in the .vho file.
An example .vho file is shown below.
component_name.coe
component_name.xco
component_name.edn
component_name.vho
component_name.mif
ASCII data file defining the coeffi-
cient values for FIR filters and
initialization values for memory
modules
CORE Generator file containing the
parameters used to generate the
customized CORE
EDIF implementation netlist for the
CORE
VHDL template file
Memory Initialization Module for
Virtex Block RAM modules
Design Methodologies - HDL Flow
--
--
--
--
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