DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 284

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
B-12
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•
You can create a Pad to Setup or Clock to Pad offset constraint with
the Constraints Editor.
There are basically three types of offset specifications.
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•
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Since the global and group OFFSET constraints are not associated
with a single data net or component, these two types can also be
entered on a TIMESPEC symbol in the design netlist with Tsid. See
the “Using Timing Constraints” in the Development System Reference
Guide for details.
In the following example, the OFFSET constraint is applied to a net
that connects with a PAD (as shown in the figure later in this section).
It defines the delay of a signal relative to a clock and is only valid for
registered data paths. The OFFSET constraint specifies the signal
delay external to the chip, allowing the implementation tools to auto-
matically adjust relevant internal delays (CLK buffer and distribution
delays) to accommodate the external delay specified with the
following.
In analyzing OFFSET paths, the Xilinx timing tools adjust the
PERIOD associated with the constrained synchronous element based
on both the timing specified in the OFFSET constraint and the delay
of the referenced clock signal. In the following figure, assume a delay
of 8 ns for the signal CLK to arrive at the CLB, a 5 ns setup time for
ADD0, and a 14 ns OFFSET delay for the signal ADD0. Assume a
period of 40 ns is specified. The Foundation tools allocate 29 ns for
the signal ADD0 to arrive at the CLB input pin (40 ns - 14 ns + 8 ns -
5 ns = 29 ns).
Calculate whether a setup time is being violated at a flip-flop
whose data and clock inputs are derived from external nets.
Specify the delay of an external output net derived from the Q
output of an internal flip-flop being clocked from an external
device pin.
Global
Specific
Group
# Net form of the OFFSET timing constraint
NET ADD0_IN OFFSET = IN 14 AFTER CLK ;
Xilinx Development System