DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 164
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DS-FND-BSX-PC
Manufacturer Part Number
DS-FND-BSX-PC
Description
FOUNDATION BASE SYS W/SYN EXPRES
Manufacturer
Xilinx Inc
Type
Foundation Systemr
Datasheet
1.DS-FND-BSX-PC.pdf
(330 pages)
Specifications of DS-FND-BSX-PC
For Use With/related Products
Xilinx Programmable Logic Devices
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1185
- Current page: 164 of 330
- Download datasheet (3Mb)
Foundation Series 2.1i User Guide
6-8
3.
4.
In the Synthesis Options dialog box, set the Default FSM
Encoding style, XNF Bus Style, and Default Frequency. Check the
Export Timing Constraint box if you want to have timing
and pin location constraints entered after the elaboration step to
be automatically exported to place and route tools.
For FSM Encoding style, use the following guidelines for best
results.
•
•
Refer to the “Selecting a Netlist Format” section of the “Design
Methodologies - HDL Flow” chapter for information on setting
the “Export schematic to” option.
Click OK when all desired options are set.
To synthesize the design, click the Synthesis button on the
Flow tab. This opens the Synthesis/Implementation dialog box.
In the Synthesis/Implementation dialog box, you can do the
following.
•
If your target device is an FPGA, choose One Hot.
If your target device is a CPLD, choose Binary.
Select the name of the top-level entity or module from which
processing of the design hierarchy should begin
Xilinx Development System
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