DS-FND-BSX-PC Xilinx Inc, DS-FND-BSX-PC Datasheet - Page 241

• Manufacturer Part Number: DS-FND-BSX-PC
• Description: FOUNDATION BASE SYS W/SYN EXPRES
• Manufacturer: Xilinx Inc
• Type: Foundation Systemr

Specifications of DS-FND-BSX-PC

• For Use With/related Products: Xilinx Programmable Logic Devices
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1185

Foundation Series 2.1i User Guide
FPGA Editor
CPLD ChipViewer
Locking Device Pins
Alternatively, you can invoke the Floorplanner after running the
automatic place and route tools to view and possibly improve the
results of the automatic implementation.
The FPGA Editor is a graphical application for displaying and
configuring FPGAs. You can use the FPGA Editor to place and route
critical components before running the automatic place and route
tools on your designs. You can also use the FPGA Editor to manually
finish placement and routing if the routing program does not
completely route your design. In addition, the FPGA Editor reads
from and writes to the Physical Constraints File (PCF).
For a description of the FPGA Editor, see the FPGA Editor Guide, an
online book.
You can access the FPGA Editor through Tools
tion
The ChipViewer provides a graphical view of the CPLD fitting
report. With this tool you can examine inputs and outputs, macrocell
details, equations, and pin assignments. You can examine both pre-
fitting and post-fitting results.
More information on using the CPLD ChipViewer is available in that
tool’s online help (Tools
Viewer
Viewer.
You can automatically generate pin locking constraints in your UCF
file for use with other Xilinx implementation tools. Pinout informa-
tion is taken from a placed NCD file for FPGAs or a fitted GYD file
for CPLDs.
To lock device pins, do the following.
1.
Foundation Help Contents
From the Versions tab in the Project Manager window, select an
implementation revision.
FPGA Editor on the Project Manager’s menu bar.
Help) or from the Umbrella Help menu accessed by Help
Implementation
Advanced Tools
Design Implementation
CPLD Chip-
Implementa-
Chip-
11-35