DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1292

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 23 Flash Memory
(6) Flash Transfer Destination Address Register (FTDAR)
Rev. 3.00 May 17, 2007 Page 1234 of 1582
REJ09B0181-0300
Bit
7
6 to 0
FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded.
Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00
which points to the start address (H'FFFF9000) in on-chip RAM.
Bit Name
TDER
TDA[6:0]
Initial
Value
0
All 0
Initial value:
R/W:
Bit:
R/W
R/W
R/W
TDER
R/W
7
0
R/W
6
0
Description
Transfer Destination Address Setting Error
This bit is set to 1 when there is an error in the download
start address set by bits 6 to 0 (TDA6 to TDA0). Whether
the address setting is erroneous or not is tested by
checking whether the setting of TDA6 to TDA0 is in the
range of H'00 to H'04 after setting the SCO bit in FCCS
to 1 and performing download. Before setting the SCO
bit to 1 be sure to set the FTDAR value between H'00 to
H'04 as well as clearing this bit to 0.
0: Setting of TDA6 to TDA0 is normal
1: Setting of TDER and TDA6 to TDA0 is H'05 to H'FF
Transfer Destination Address
These bits specify the download start address. A value
from H'00 to H'04 can be set to specify the download
start address in on-chip RAM in 2-kbyte units.
A value from H'05 to H'7F cannot be set. If such a value
is set, the TDER bit (bit 7) in this register is set to 1 to
prevent download from being executed.
H'00: Download start address is set to H'FFFF9000
H'01: Download start address is set to H'FFFF9800
H'02: Download start address is set to H'FFFFA000
H'03: Download start address is set to H'FFFFA800
H'04: Download start address is set to H'FFFFB000
H'05 to H'7F: Setting prohibited. If this value is set, the
R/W
and download has been aborted
5
0
R/W
4
0
TDA[6:0]
R/W
TDER bit (bit 7) is set to 1 to abort the
download processing.
3
0
R/W
2
0
R/W
1
0
R/W
0
0