DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 828
DF70844AD80FPV
Manufacturer Part Number
DF70844AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70844AD80FPV
Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
16KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70844AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 Serial Communication Interface (SCI)
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the
2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is
4. After the end of serial transmission, the SCK pin is held in the high state.
Figure 15.11 shows an example of SCI transmit operation.
Rev. 3.00 May 17, 2007 Page 770 of 1582
REJ09B0181-0300
Synchronization
SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers
the data from SCTDR to the transmit shift register (SCTSR).
transmission. If the transmit-data-empty interrupt enable bit (TIE) in the serial control register
(SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data is
output from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7).
0, the data is transferred from SCTDR to SCTSR and serial transmission of the next frame is
started, If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the MSB (bit 7) is sent, and
then the TXD pin holds the states.
If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.
Serial data
TDRE
TEND
clock
Transfer direction
TXI interrupt
request
Figure 15.11 Example of SCI Transmit Operation
Bit 0
Data written to SCTDR
and TDRE flag cleared
to 0 by TXI interrupt handler
LSB
Bit 1
One frame
TXI interrupt
request
Bit 7
MSB
Bit 0
Bit 1
Bit 6
TEI interrupt
request
Bit 7
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