DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1389

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.3.2
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit
6 to 0
Bit
7
6
5
4
Standby Control Register 2 (STBCR2)
Bit Name

Bit Name
MSTP7
MSTP6

MSTP4
Initial value:
Initial
Value
All 0
Initial
Value
0
0
1
1
R/W:
Bit:
MSTP
R/W
7
0
7
R/W
R
R/W
R/W
R/W
R
R/W
MSTP
R/W
6
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Module Stop Bit 7
When this bit is set to 1, the supply of the clock to the
RAM is halted.
0: RAM operates
1: Clock supply to RAM halted
Module Stop Bit 6
When this bit is set to 1, the supply of the clock to the
ROM is halted.
0: ROM operates
1: Clock supply to ROM halted
Reserved
This bit is always read as 1. The write value should
always be 1.
Module Stop Bit 4
When this bit is set to 1, the supply of the clock to the
DTC is halted.
0: DTC operates
1: Clock supply to the DTC halted
R
5
1
-
MSTP
R/W
4
1
4
MSTP
R/W
3
1
3
Rev. 3.00 May 17, 2007 Page 1331 of 1582
R
2
0
-
R
1
0
-
Section 26 Power-Down Modes
R
0
0
-
REJ09B0181-0300