DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 354

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.5.4
The number of cycles from CSn assertion to RD, WRxx assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from RD, WRxx negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles, RD and WRxx are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
Rev. 3.00 May 17, 2007 Page 296 of 1582
REJ09B0181-0300
CSn Assert Period Extension
Read
Write
Note: * The waveform for DACKn is when active low is specified.
D31 to D0
D31 to D0
A29 to A0
Figure 9.10 CSn Assert Period Extension
DACKn*
RDWR
WRxx
CSn
RD
CK
BS
Th
T1
T2
Tf