DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 221

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.4.7
Break Condition Specified for L Bus Instruction Fetch Cycle:
(Example 1-1)
• Register specifications
(Example 1-2)
• Register specifications
BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
<Channel B>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
A user break occurs after an instruction of address H'00000404 is executed or before
instructions of addresses H'00008010 to H'00008016 are executed.
BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000,
BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056,
BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008
Specified conditions: Channel A/channel B sequential mode
<Channel A>
Address:
Data:
Bus cycle: L bus/instruction fetch (before instruction execution)/read/word
Usage Examples
H'00000404, Address mask: H'00000000
H'00000000, Data mask: H'00000000
included in the condition)
H'00008010, Address mask: H'00000006
H'00000000, Data mask: H'00000000
included in the condition)
H'00037226, Address mask: H'00000000
H'00000000, Data mask: H'00000000
Rev. 3.00 May 17, 2007 Page 163 of 1582
Section 7 User Break Controller (UBC)
REJ09B0181-0300