DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 443

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.2
The external pins for the DMAC are described below. Table 10.1 lists the configuration of the pins
that are connected to external bus. The DMAC has pins for 4 channels for external bus use.
Table 10.1 Pin Configuration
Channel Pin Name
0
1
2
3
Input/Output Pins
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
DMA transfer request
DMA transfer request
acknowledge
DMA transfer request
DMA transfer request
acknowledge
Symbol
DREQ0
DACK0
TEND0
DREQ1
DACK1
TEND1
DREQ2
DACK2
DREQ3
DACK3
I/O
Input
Output DMA transfer request acknowledge
Output DMA transfer end output for channel 0
Input
Output DMA transfer request acknowledge
Output DMA transfer end output for channel 1
Input
Output DMA transfer request acknowledge
Input
Output DMA transfer request acknowledge
Section 10 Direct Memory Access Controller (DMAC)
Function
DMA transfer request input from
external device to channel 0
output from channel 0 to external
device
DMA transfer request input from
external device to channel 1
output from channel 1 to external
device
DMA transfer request input from
external device to channel 2
output from channel 2 to external
device
DMA transfer request input from
external device to channel 3
output from channel 3 to external
device
Rev. 3.00 May 17, 2007 Page 385 of 1582
REJ09B0181-0300