DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 271

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.8
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or on completion of a single data transfer or a single block data transfer with the DISEL
bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is
generated. These interrupts to the CPU are subject to CPU mask level and priority level control in
the interrupt controller. For details, refer to section 6.8, Data Transfer with Interrupt Request
Signals.
8.9
8.9.1
Operation of the DTC can be disabled or enabled using the standby control register. The initial
setting is for operation of the DTC to be disabled. DTC operation is disabled in module standby
mode but register access is available. Module standby mode cannot be set while the DTC is
activated. Before entering software standby mode or module standby mode, all DTCER registers
must be cleared. For details, refer to section 26, Power-Down Modes.
8.9.2
Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must
not be cleared to 0.
8.9.3
To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it.
While DTC transfer is in progress, do not modify the DTCE bits.
8.9.4
When chain transfer is used, clearing of the activation source or DTCER is performed when the
last of the chain of data transfers is executed. SCI, SCIF, SSU, I
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
relevant register.
Interrupt Sources
Usage Notes
Module Standby Mode Setting
On-Chip RAM
DTCE Bit Setting
Chain Transfer
Rev. 3.00 May 17, 2007 Page 213 of 1582
Section 8 Data Transfer Controller (DTC)
2
C2, and A/D converter
REJ09B0181-0300