DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 588

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Cascaded Operation Example (c): Figure 11.23 illustrates the operation when TCNT_1 and
TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include
the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions,
respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected
both the rising and falling edges for the input capture timing. Under these conditions, the ORed
result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture
conditions.
Cascaded Operation Example (d): Figure 11.24 illustrates the operation when TCNT_1 and
TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A
pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1
have selected TGRA_0 compare match or input capture occurrence for the input capture timing
while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input
capture timing.
Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture
occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture
condition although the I2AE bit in TICCR has been set to 1.
Rev. 3.00 May 17, 2007 Page 530 of 1582
REJ09B0181-0300
TGRA_1
TGRA_2
TCNT_1
TIOC1A
TIOC2A
H'FFFF
H'C256
H'9192
H'6128
H'2064
H'0000
TCNT_2 value
Figure 11.23 Cascaded Operation Example (c)
H'0512
H'0512
H'6128
H'0513
H'2064
H'0513
H'C256
H'0514
H'0514
H'9192
Time