DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 13

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.3
8.4
8.5
8.6
8.7
8.8
8.9
Section 9 Bus State Controller (BSC)................................................................217
9.1
9.2
9.3
9.4
8.2.10 Bus Function Extending Register (BSCEHR) ...................................................... 183
Activation Sources ............................................................................................................. 184
Location of Transfer Information and DTC Vector Table ................................................. 184
Operation ........................................................................................................................... 189
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 DTC Activation Priority Order ............................................................................. 209
DTC Activation by Interrupt.............................................................................................. 210
Examples of Use of the DTC ............................................................................................. 211
8.7.1
8.7.2
Interrupt Sources................................................................................................................ 213
Usage Notes ....................................................................................................................... 213
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10 Conflict between NMI Interrupt and DTC Activation .......................................... 215
8.9.11 Operation when a DTC Activation Request is Cancelled While in Progress........ 215
Features.............................................................................................................................. 217
Input/Output Pins ............................................................................................................... 220
Area Overview ................................................................................................................... 222
9.3.1
9.3.2
Register Descriptions ......................................................................................................... 241
Transfer Information Read Skip Function ............................................................ 194
Transfer Information Writeback Skip Function .................................................... 195
Normal Transfer Mode ......................................................................................... 195
Repeat Transfer Mode........................................................................................... 196
Block Transfer Mode ............................................................................................ 198
Chain Transfer ...................................................................................................... 199
Operation Timing.................................................................................................. 201
Number of DTC Execution Cycles ....................................................................... 204
DTC Bus Release Timing ..................................................................................... 206
Normal Transfer Mode ......................................................................................... 211
Chain Transfer when Counter = 0......................................................................... 211
Module Standby Mode Setting ............................................................................. 213
On-Chip RAM ...................................................................................................... 213
DTCE Bit Setting.................................................................................................. 213
Chain Transfer ...................................................................................................... 213
Transfer Information Start Address, Source Address,
and Destination Address ....................................................................................... 214
Access to DMAC or DTC Registers through DTC............................................... 214
Notes on IRQ Interrupt as DTC Activation Source .............................................. 214
Notes on SCI and SCIF as DTC Activation Sources ............................................ 214
Clearing Interrupt Source Flag.............................................................................. 214
Area Division........................................................................................................ 222
Address Map ......................................................................................................... 222
Rev. 3.00 May 17, 2007 Page xiii of lviii