DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1613

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Item
Figure 16.18 Sample Flowchart for
Transmitting/Receiving Serial
Data
16.7.8 FER Flag and PER Flag of
Serial Status Register (SCFSR)
17.3.6 SS Control Register 2
(SSCR2)
Table 17.6 Communication Modes
and Pin States of SSCK Pin
Page Revision (See Manual for Details)
849
857
872
880
Amended
Added
Amended
SSCR2 is a register that enables/disables the open-
drain outputs of the SSO, SSI, SSCK, and SCS pins,
selects the assert timing of the SCS pin, data output
timing of the SSO pin, and set timing of the TEND bit.
Deleted
Bit
7 to 5 
Communication
Mode
SSU
communication
mode
Clock
synchronous
communication
mode
Bit Name
No
Start of transmission and reception
Write transmit data to SCFTDR,
and TEND flag in SCFSR to 0
Read TDFE flag in SCFSR
after reading them as 1
and clear TDFE flag
Initialization
TDFE = 1?
Initial
Value R/W Description
All 0
Yes
Rev. 3.00 May 17, 2007 Page 1555 of 1582
MSS
0
1
0
1
R
Register Setting
[1]
Reserved
These bits are always read as 0.
The write value should always be 0.
SCKS
0
1
0
1
0
1
0
1
[1] SCIF status check and transmit data
[2] Receive error handling:
Read SCFSR and check that the
write:
TDFE flag and the TEND flag are set
to 1, then write transmit data to
SCFTDR, and clear the TDFE flag
and the TEND flag to 0. The transition
of the TDFE flag from 0 to 1 can also
be identified by a TXIF interrupt.
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
to 1.
Read the ORER flag in SCLSR to
REJ09B0181-0300
Pin State
SSCK
Input
Output
Input
Output