DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1399

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.6
26.6.1
This LSI shifts from a program execution state to deep software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR1 is 1 and the STBYMD bit in STBCR6 is 0.
However, deep software standby mode cannot be entered when the bus is released (low-level input
to BREQ pin). Execute the SLEEP instruction after halting the DMAC and DTC. In deep software
standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Furthermore, the internal power supply of this LSI is turned off.
The contents of the CPU registers and the data of the on-chip RAM become undefined. The
registers of on-chip peripheral modules are initialized. For details on the pin states in deep
software standby mode, refer to appendix A, Pin States.
The procedure for a transition to deep software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. If the DMAC and DTC are operating, stop their operation.
3. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level
4. After setting the STBY bit in STBCR1 to 1 and clearing the STBYMD bit in STBCR6 to 0,
5. Deep software standby mode is entered, the clocks within this LSI are halted, and the internal
26.6.2
Deep software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin
low until the clock oscillation settles.
input to BREQ pin).
execute the SLEEP instruction.
power supply of this LSI is turned off.
Deep Software Standby Mode
Transition to Deep Software Standby Mode
Canceling Deep Software Standby Mode
Rev. 3.00 May 17, 2007 Page 1341 of 1582
Section 26 Power-Down Modes
REJ09B0181-0300