DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 860

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7
SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR
data, and the lower 8 bits indicate the status flag indicating SCIF operating state.
The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND,
TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written.
Initial value:
Rev. 3.00 May 17, 2007 Page 802 of 1582
REJ09B0181-0300
Bit
15 to 12
11 to 8
Note:
R/W:
Bit:
*
To clear the flag, only 0 can be written after reading 1.
Serial Status Register (SCFSR)
15
R
0
Bit Name
PER[3:0]
FER[3:0]
14
R
0
PER[3:0]
13
R
0
Initial
value
0000
0000
12
R
0
11
R
0
R/W
R
R
10
R
0
FER[3:0]
R
9
0
Description
Number of Parity Errors
Indicate the number of data including a parity error in
the receive data stored in the receive FIFO data
register (SCFRDR). After the ER bit in SCFSR is set
to 1, the value indicated by bits 15 to 12 indicates the
number of parity errors in SCFRDR. When parity
errors have occurred in all 16-byte receive data in
SCFRDR, PER3 to PER0 show 0.
Number of Framing Errors
Indicate the number of data including a framing error
in the receive data stored in SCFRDR. After the ER
bit in SCFSR is set to 1, the value indicated by bits 11
to 8 indicates the number of framing errors in
SCFRDR. When framing errors have occurred in all
16-byte receive data in SCFRDR, FER3 to FER0
show 0.
R
8
0
R/(W)* R/(W)* R/(W)* R/(W)*
ER
7
0
TEND
6
1
TDFE
5
1
BRK
4
0
FER
R
3
0
PER
R
2
0
R/(W)* R/(W)*
RDF
1
0
DR
0
0