DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 468

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.9 shows an example of DMA transfer timing in single address mode.
Bus Modes: There are two bus modes: cycle steal mode and burst mode. Select the mode in the
TB bits in the channel control register (CHCR).
• Cycle-Steal Mode
Rev. 3.00 May 17, 2007 Page 410 of 1582
REJ09B0181-0300
 Normal mode
Figure 10.10 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
In cycle-steal normal mode, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to the
other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the
transfer request source, transfer source, and transfer destination.
D31 to D0
D31 to D0
A29 to A0
A29 to A0
Figure 10.9 Example of DMA Transfer Timing in Single Address Mode
DACKn
DACKn
WRxx
CSn
CSn
RD
CK
CK
(b) External memory space (ordinary memory) → external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
Data output from external memory space
DACK signal (active-low) to external device with DACK