DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1546

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Appendix
[Legend]
I:
O:
H:
L:
Z:
K:
Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6
Rev. 3.00 May 17, 2007 Page 1488 of 1582
REJ09B0181-0300
Input
Output
High-level output
Low-level output
High-impedance
Input pins become high-impedance, and output pins retain their state.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set
4. Becomes high-impedance when the MZIZDH bit in the high-current port control register
5. Becomes high-impedance when the MZIZDL bit in the high-current port control register
6. Becomes high-impedance when the MZIZEH bit in the high-current port control register
7. Becomes high-impedance when the MZIZEL bit in the high-current port control register
8. Becomes input during a power-on reset. Pull-up to prevent erroneous operation. Pull-
9. Pulled-up inside the LSI when there is no input.
(STBCR6) is set to 1.
to 1.
to 1.
(HCPCR) is cleared to 0.
(HCPCR) is cleared to 0.
(HCPCR) is cleared to 0.
(HCPCR) is cleared to 0.
down with a resistance of at least 1 MΩ as required.