DF70844AD80FPV Renesas Electronics America, DF70844AD80FPV Datasheet - Page 1629

• Manufacturer Part Number: DF70844AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70844AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 256KB (256K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Item
Table 28.8 Bus Timing
Page Revision (See Manual for Details)
1418
to
1420
Amended
Notes: 3. The operation of the F-ZTAT version supporting full functions
Item
Address delay time 1
Address delay time 2
BS delay time
CS delay time
Read write delay time
Read strobe delay time
Read data setup time 1
Read data setup time 2
Read data setup time 3
Read data access time
Access time from read strobe
Write strobe delay time 1
Write strobe delay time 2
Write data delay time 1
Write data delay time 2
WAIT setup time
WAIT hold time
RAS delay time
CAS delay time
DQM delay time
CKE delay time
AH delay time
Multiplexed address delay time t
DACK, TEND delay time
FRAME delay time
ICIORD delay time
ICIOWR delay time
of E10A is guaranteed between temperatures of 0 to +50°C.
Rev. 3.00 May 17, 2007 Page 1571 of 1582
Symbol Min.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AD1
AD2
BSD
CSD
RWD
RSD
RDS1
RDS2
RDS3
ACC
OE
WSD1
WSD2
WDD1
WDD2
WTS
WTH
RASD
CASD
DQMD
CKED
AHD
MAD
DACD
FMD
ICRSD
ICWSD
*
*
2
2
1
1/2t
—
1
1
1/2t
1/2t
19
1/2t
t
(n +1.5) − 33
t
(n + 1) − 31
1/2t
—
—
—
1/2t
1/2t
1
1
1
1
1/2t
—
1
1
1/2t
1/2t
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
×
×
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
+ 1
+ 1
+ 18
+ 18
+ 1
+ 17
+ 7
+ 1
+ 1
+ 1
REJ09B0181-0300
Max.
18
1/2t
18
18
18
1/2t
—
—
—
—
—
1/2t
18
18
18
—
—
18
18
18
18
1/2t
18
18
18
1/2t
1/2t
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
Bcyc
+18
+ 18
+ 18
+ 18
+ 18
+ 18